Blind Source Separation in Nonlinear Mixture for Colored Sources Using Signal Derivatives

International audienceWhile Blind Source Separation (BSS) for linear mixtures has been well studied, the problem for nonlinear mixtures is still thought not to have a general solution. Each of the techniques proposed for solving BSS in nonlinear mixtures works mainly on specific models and cannot be generalized for many other realistic applications. Our approach in this paper is quite different and targets the general form of the problem. In this advance, we transform the nonlinear problem to a time-variant linear mixtures of the source derivatives. The proposed algorithm is based on separating the derivatives of the sources by a modified novel technique that has been developed and specialized for the problem, which is followed by an integral operator for reconstructing the sources. Our simulations show that this method separates the nonlinearly mixed sources with outstanding performance; however , there are still a few more steps to be taken to get to a comprehensive solution which are mentioned in the discussion

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

On the Achievability of Cram\'er-Rao Bound In Noisy Compressed Sensing

Recently, it has been proved in Babadi et al. that in noisy compressed sensing, a joint typical estimator can asymptotically achieve the Cramer-Rao lower bound of the problem.To prove this result, this paper used a lemma,which is provided in Akcakaya et al,that comprises the main building block of the proof. This lemma is based on the assumption of Gaussianity of the measurement matrix and its randomness in the domain of noise. In this correspondence, we generalize the results obtained in Babadi et al by dropping the Gaussianity assumption on the measurement matrix. In fact, by considering the measurement matrix as a deterministic matrix in our analysis, we find a theorem similar to the main theorem of Babadi et al for a family of randomly generated (but deterministic in the noise domain) measurement matrices that satisfy a generalized condition known as The Concentration of Measures Inequality. By this, we finally show that under our generalized assumptions, the Cramer-Rao bound of the estimation is achievable by using the typical estimator introduced in Babadi et al

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Interconnects for DNA, quantum, in-memory and optical computing: insights from a panel discussion

The computing world is witnessing a proverbial Cambrian explosion of emerging paradigms propelled by applications such as Artificial Intelligence, Big Data, and Cybersecurity. The recent advances in technology to store digital data inside a DNA strand, manipulate quantum bits (qubits), perform logical operations with photons, and perform computations inside memory systems are ushering in the era of emerging paradigms of DNA computing, quantum computing, optical computing, and in-memory computing. In an orthogonal direction, research on interconnect design using advanced electro-optic, wireless, and microfluidic technologies has shown promising solutions to the architectural limitations of traditional von-Neumann computers. In this article, experts present their comments on the role of interconnects in the emerging computing paradigms and discuss the potential use of chiplet-based architectures for the heterogeneous integration of such technologies.This work was supported in part by the US NSF CAREER Grant CNS-1553264 and EU H2020 research and innovation programme under Grant 863337.Peer ReviewedPostprint (author's final draft

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

The grand challenge of scaling up quantum computers requires a full-stack architectural standpoint. In this position paper, we will present the vision of a new generation of scalable quantum computing architectures featuring distributed quantum cores (Qcores) interconnected via quantum-coherent qubit state transfer links and orchestrated via an integrated wireless interconnect.Comment: 5 pages, 2 figures, accepted for presentation at the IEEE International Symposium on Circuits and Systems (ISCAS) 202

CMOS-based cryogenic control of silicon quantum circuits

The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, a major bottleneck appears between the quantum chip in a dilution refrigerator and the room temperature electronics. Advanced lithography supports the fabrication of both CMOS control electronics and qubits in silicon. When the electronics are designed to operate at cryogenic temperatures, it can ultimately be integrated with the qubits on the same die or package, overcoming the wiring bottleneck. Here we report a cryogenic CMOS control chip operating at 3K, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20mK. We first benchmark the control chip and find electrical performance consistent with 99.99% fidelity qubit operations, assuming ideal qubits. Next, we use it to coherently control actual silicon spin qubits and find that the cryogenic control chip achieves the same fidelity as commercial instruments. Furthermore, we highlight the extensive capabilities of the control chip by programming a number of benchmarking protocols as well as the Deutsch-Josza algorithm on a two-qubit quantum processor. These results open up the path towards a fully integrated, scalable silicon-based quantum computer

A wideband 60 GHz class-E/F2 power amplifier in 40nm CMOS

2015 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, Phoenix, Arizona, USA, 17 - 19 May 2015This paper presents a fully integrated 60 GHz power amplifier in 40nm CMOS that reaches the highest reported product of power-added efficiency and bandwidth. It is achieved through low/moderate coupling-factor transformers in the preliminary stages and a proper second harmonic termination of the output stage, such that it can operate as a class-E/F2 switched-mode PA at the saturation point. The three-stage PA delivers 17.9dBm saturated output power with 20% peak PAE. It demonstrates a bandwidth of 9.7 GHz with a peak gain of 21.6 dB.European Research Counci